1. Field of the Invention
This invention relates to memory apparatus, and in particular but not exclusively to memory apparatus for video data processing.
2. Description of the Prior Art
In known memory architectures, a fixed memory cycle is generally defined such that read access and write access to the memory is performed in accordance with a predetermined and unvariable scheme, buffers and latches being provided to set the required data routing.
The use of such a fixed memory cycle can be disadvantageous in certain circumstances, for example when the number of required read operations exceeds the number of write operations, or vice versa. In this case, slots in the memory cycles allotted to a particular operation, for example write slots, will often remain vacant if the requirement is for a greater number for another operation, for example reading. This represents uneconomic use of the memory and results in an overall decrease in processing speed.
One area in which the above problem arises is in video data processing, for example for manipulation of image data from a number of different video data channels. In such a video data processing system, it may for example be necessary to write in data from a greater number of channels than are being read from at that time. Alternatively, a greater number of channels may need to be read rather than written. When the video data is being processed in real time, the decrease in processing speed resulting from the "wasted" access slots in a fixed memory cycle scheme represents a considerable disadvantage.